Implementasi pada FPGA atas Soft-Output Viterbi Algorithm (SOVA) untuk Pengawasandian Turbo

Daryus Chandra, Budi Setiyanto, Sri Suning Kusumawardani

Abstract


Abstract—There are two kinds of algorithm that widely used for decoding the turbo codes, those are Soft-Output Viterbi Algorithm (SOVA) and Maximum A Posteriori Algorithm (MAP). MAP Algorithm gives a better result on error correcting capability, but the consequence it has higher complexity algorithm, in contrary to SOVA. This paper presented a design for decoding turbo codes using SOVA with Very high-speed integrated circuit Hardware Description Language (VHDL) as the modelling program and the design is implemented on the FPGA. Implementation result shows that SOVA occupies 159 slices or 3% of the available slices in Xilinx Spartan-3E, 105 flip flop (1%), 278 LUT (2%), and 141 IOB (60%) with maximum frequency clock is 43,384 MHz. FPGA implementation of SOVA decoder is able to correct up to six non-burst error symbols from 16 received symbols, but SOVA fails to perform its errorcorrecting capability for three consecutive error symbols. SOVA decoder can be implemented for turbo decoding by combining SOVA decoder with interleaver and deinterleaver.

Intisari—Terdapat dua algoritma yang digunakan untuk mengawasandikan sandi turbo yaitu Soft-Output Viterbi Algorithm (SOVA) dan Maximum A Posteriori Algorithm (MAP). Algoritma MAP memberikan kemampuan koreksi yang sedikit lebih baik daripada SOVA, namun dengan kompleksitas algoritma MAP yang lebih tinggi jika dibandingkan dengan SOVA. Dalam penelitian ini dipaparkan rancangan pengawasandian turbo dengan Soft-Output Viterbi Algorithm (SOVA) dengan menggunakan Very high speed integrated circuit Hardware Description Language (VHDL). Hasil implementasi menunjukkan bahwa pengawasandi SOVA membutuhkan 159 slices atau 3% dari keseluruhan slices yang tersedia pada FPGA Xilinx Spartan-3E, 105 flip flop (1%), 278 LUT (2%), dan 141 IOB (60%) dengan frekuensi clock maksimum yang dapat dicapai adalah 43,384 MHz. Pengawasandi SOVA mampu melakukan koreksi hingga enam simbol galat tipe acak dari 16 runtun simbol namun pengawasandi SOVA gagal melakukan koreksi galat apabila terdapat tiga buah galat deburan muncul pada runtun kata sandi. Implementasi FPGA atas pengawasandi SOVA dapat diimplementasikan dalam sistem pengawasandian turbo dengan menambahkan blok interleaver dan blok deinterleaver pada blok pengawasandi SOVA.

Kata Kunci— Penyandian kanal, teknik koreksi galat, sandi turbo, SOVA, FPGA


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References


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DOI: http://dx.doi.org/10.22146/jnteti.v2i4.100

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